外文翻译---基于DDS参数可调谐波信号发生器的研究 本文关键词：可调，外文，谐波，翻译，参数
外文翻译---基于DDS参数可调谐波信号发生器的研究 本文简介：附录AResearchofParameterAdjustableHarmonicSignalGeneratorBasedonDDSLIWeiCollegeofComputerandInformationEngineeringHohaiUniversityChangzhou,213022,China[
外文翻译---基于DDS参数可调谐波信号发生器的研究 本文内容：
附录A
Research
of
Parameter
Adjustable
Harmonic
Signal
Generator
Based
on
DDS
LI
Wei
College
of
Computer
and
Information
Engineering
Hohai
University
Changzhou,213022,China
[email protected]
ZHANG
Jinbo
College
of
Computer
and
Information
Engineering
Hohai
University
Changzhou,213022,China
[email protected]
Abstract
Harmonic
signal
generator
whose
frequency,phase
and
harmonic
proportion
are
adjustable
is
designed
for
the
detecting
equipment
of
power
system.
The
principle
of
DDS
and
the
design
requirement
are
introduced.
Then
the
algorithm
of
ROM
compression
based
on
the
symmetry
of
sine
wave
is
expounded.
Finally,using
Altera
FPGA,the
detail
design
of
the
whole
system
is
presented
and
test
waveforms
are
given.
Test
results
indicate
that
the
system
fulfils
the
design
requirements.
1.
Introduction
An
ideal
power
system
supplies
power
with
sine
wave,but
the
practical
waveform
of
power
supply
often
has
many
harmonic
components.
The
basic
reason
of
harmonic
is
that
the
power
system
supplies
power
to
the
electrical
equipment
with
nonlinear
characteristic.
These
nonlinear
loads
feed
higher
harmonic
back
to
the
power
supply,and
make
the
waveform
of
current
and
voltage
in
power
system
produce
serious
distortion.
In
the
detection
field
of
power
system,standard
signal
generators
which
can
simulate
the
power
harmonic
are
highly
needed
to
calibrate
the
power
detecting
equipment,such
as
phase
detector,PD
detector,and
so
on.
So
the
research
of
parameter
adjustable
harmonic
signal
generator
provides
the
exact
basis
for
the
stable
operation
of
power
detecting
equipment,and
has
great
economic
benefit
and
social
value.
2.
Principle
of
direct
digital
synthesis
Direct
digital
synthesis
(DDS)
is
a
new
frequency
synthesis
technology
which
directly
synthesizes
waveform
on
the
basis
of
phase.
Using
the
relationship
between
phase
and
amplitude,the
phase
of
waveform
is
segmented
and
assigned
relevant
addresses.
In
each
clock
period,these
addresses
are
extracted
and
the
relevant
amplitudes
are
sampled.
The
envelope
of
these
sampled
amplitudes
is
the
expected
waveform.
If
the
clock
frequency
is
constant,the
frequency
of
output
signal
is
adjustable
with
different
extracted
steps
of
addresses.
DDS
is
composed
of
phase
accumulator,ROM
table,DAC
and
LPF.
In
each
clock
period,the
output
of
phase
accumulator
is
accumulated
with
frequency
control
word,and
high
L-bit
of
the
output
are
used
as
address
to
query
the
ROM
table.
In
the
ROM,these
addresses
are
converted
to
the
sampled
amplitudes
of
the
expected
waveform.
Then
DAC
converts
the
sampled
amplitudes
to
ladder
wave.
In
the
LPF,the
ladder
wave
is
smoothed,and
the
output
is
the
continuous
analog
waveform.
Suppose
that
the
clock
frequency
is
fc,frequency
control
word
is
K,phase
accumulator
is
N-bit,then
output
frequency
is
fout=(K/2N)fc,frequency
resolution
is
Δfmin=fc/2N.
According
to
the
Nyquist
Sample
Criterion,output
frequency
upper
limit
is
fmax<0.5fc.
Because
of
the
non-ideal
characteristic
of
LPF,output
frequency
upper
limit
of
DDS
is
fmax=0.4fc.
3.
Scheme
design
3.1.
Design
requirements
The
goal
of
the
system
is
to
design
a
harmonic
signal
generator,whose
frequency,phase
and
harmonic
proportion
are
adjustable.
The
output
waveform
is
composed
of
fundamental
wave,3th
harmonic,5th
harmonic
and
7th
harmonic.
Frequency
resolution
is
1Hz.
The
adjustable
range
of
initial
phase
is
0~2π
and
its
resolution
is
1o.
The
adjustable
range
of
harmonic
proportion
is
0~50%
and
its
resolution
is
1%.
According
to
the
design
requirements,system
clock
frequency
is
15MHz
and
phase
accumulator
is
24-bit.
In
order
to
make
the
most
of
EAB,211×8
bits
ROM
table
is
adopted.
11-bit
phase
control
word
is
used
to
meet
the
requirement
of
initial
phase
resolution.
7-bit
proportion
control
word
is
adopted
to
realize
the
setting
of
harmonic
proportion.
3.2.
Algorithm
of
ROM
compression
As
is
known,phase
truncation
error
is
the
main
factor
of
output
waveform
distortion.
To
avoid
this,the
ROM
size
must
be
exponentially
increased,however
the
EAB
of
FPGA
is
limited.
So
the
algorithm
of
ROM
compression
based
on
the
symmetry
of
sine
wave
is
adopted
in
the
system.
Sine
wave
of
one
period
is
divided
into
4
sections:
[0~π/2]
、[π/2~π]
、[π~3π/2]
、[3π/2~2π].
Using
the
symmetry
of
sine
wave,sampled
amplitudes
of
the
first
section
are
stored
in
the
ROM
table.
By
address
conversion
and
amplitude
conversion,sampled
amplitudes
of
one
period
sine
wave
can
be
generated.
By
this
means,the
ROM
size
is
a
quarter
of
the
previous
size.
In
the
same
ROM,sampling
points
can
be
increased
by
4
times
with
this
method.
Sampled
amplitudes
of
quarter
wave
are
stored
in
the
ROM
table.
The
output
address
of
phase
accumulator
is
(L+2)-bit.
The
low
L-bit
are
used
to
query
the
ROM
table
while
the
high
2-bit
are
used
to
identify
phase
sections.
When
the
highest
bit
is
1,the
output
of
ROM
table
should
be
symmetrically
converted
by
the
amplitude
convertor.
When
the
second
highest
bit
is
1,the
L-bit
address
should
be
symmetrically
converted
by
the
address
convertor.
4.
System
design
based
on
FPGA
The
system
can
be
divided
into
two
function
modules:
sine
wave
generation
module
and
harmonic
synthesis
module.
Sine
wave
generation
module
is
the
key
part
of
the
system.
It
can
be
divided
into
phase
accumulator
module
and
ROM
compression
module
.
Altera
FPGA
EP2C5Q208C8
is
adopted
as
the
core
component
of
the
system.
VHDL
is
used
to
program
the
whole
system.
Compilation
and
simulation
are
implemented
in
Quartus
Ⅱ.
4.1.
Sine
wave
generation
module
phase
accumulator
module
is
composed
of
24-bit
accumulator
and
11-bit
adder.
Under
the
control
of
system
clock,the
output
of
24-bit
accumulator
is
accumulated
with
9-bit
frequency
control
word.
Then
11-bit
adder
adds
11-bit
phase
control
word
to
the
output
of
accumulator.
High
13-bit
of
the
final
result
are
used
as
address
to
query
the
ROM
compression
module.
ROM
compression
module
is
composed
of
address
convertor,amplitude
convertor
and
ROM
table.
13-bit
address
of
phase
accumulator
module
is
divided
into
three
parts.
The
highest
bit
is
used
as
trigger
signal
of
the
amplitude
convertor.
The
second
highest
bit
is
used
as
trigger
signal
of
the
address
convertor.
The
low
11-bit
are
used
to
query
the
ROM
table.
Then
sampled
amplitudes
of
sine
wave
are
generated.
Simulation
result
of
sine
wave
generation
module
is
shown
in
Fig.4.
Frequency
control
word
is
set
as
50
while
phase
control
word
is
set
as
180.
When
the
enable
signal
is
turned
into
low
level,the
first
output
value
is
the
waveform
data
of
address
180
in
the
ROM
table.
With
each
rising
edge
of
system
clock,the
waveform
data
of
address
180,181,182,183
are
sent
out.
The
output
values
are
respectively
76,76,77,77.
4.2.
Harmonic
synthesis
module
Harmonic
synthesis
module
implements
the
synthesis
of
fundamental
wave,3th
harmonic,5th
harmonic
and
7th
harmonic.
The
3th,5th
and
7th
harmonic
data
are
respectively
multiplied
by
their
proportion
control
words.
Then
the
results
of
multiplication
are
added
to
the
fundamental
wave
data.
The
realization
of
multiplication
is
the
emphasis
of
the
module.
Because
it
is
difficult
to
implement
the
multiplication
of
floating-point
format
on
FPGA,harmonic
proportion
is
divided
into
numerator
and
denominator.
The
numerator
is
defined
as
proportion
control
word
while
the
denominator
is
100.
Firstly,harmonic
data
is
multiplied
by
the
proportion
control
word
in
the
multiplier.
Then,the
product
of
multiplier
is
divided
by
100
in
the
divider.
Finally,the
remainder
is
excluded
and
the
quotient
is
preserved.
Using
Altera
IP
tools,the
multiplier
and
the
divider
of
harmonic
synthesis
module
are
realized.
Block
diagram
of
harmonic
synthesis
module
is
shown.
Simulation
result
of
harmonic
synthesis
module
is.
Control
words
are
set
before
2.0ms.
Fundamental
wave
frequency
is
50Hz,and
its
initial
phase
is
0o.
The
3th
harmonic
frequency
is
150Hz,initial
phase
is
45o
and
proportion
is
50%.
The
5th
harmonic
frequency
is
250Hz,initial
phase
is
90o
and
proportion
is
25%.
The
7th
harmonic
frequency
is
350Hz,initial
phase
is
135o
and
proportion
is
17%.
When
enable
signal
is
turned
into
low
level,harmonic
synthesis
module
begins
to
generate
the
harmonic
synthesis
data.
5.
Test
results
Figure
7.
Two-channel
sine
waves
(frequency
is
50Hz
and
phase
difference
is
180o)
Figure
8.
Two-channel
sine
waves
(frequency
is
50Hz
and
phase
difference
is
120o)
Figure
9.
Harmonic
synthesis
waveform
After
the
design
of
the
system,the
whole
function
is
tested.
Fig.7
shows
two-channel
sine
waves
whose
frequency
is
50Hz
and
phase
difference
is
180o.
Fig.8
shows
two-channel
sine
waves
whose
frequency
is
50Hz
and
phase
difference
is
120o.
Fig.9
shows
the
harmonic
synthesis
waveform,whose
fundamental
wave
proportion
is
100%,3th
harmonic
proportion
is
25%,and
5th
harmonic
proportion
is
10%.
Test
waveforms
indicate
that
the
parameter
adjustable
harmonic
signal
generator
fulfils
the
design
requirements.
6.
Conclusion
In
the
detection
field
of
power
system,standard
signal
generators
which
can
simulate
the
power
harmonic
are
highly
needed
to
calibrate
the
power
detecting
equipment.
To
solve
this
problem,a
harmonic
signal
generator
whose
frequency,phase
and
harmonic
proportion
are
adjustable
is
presented.
Using
Altera
FPGA,the
whole
system
is
implemented.
Test
results
indicate
that
the
adjustment
and
stabilization
precision
of
parameters
meet
the
design
requirements.
This
subject
provides
the
exact
basis
for
the
stable
operation
of
power
detecting
equipment,and
has
great
economic
benefit
and
social
value.
References
[1]
Li
Xiaoming
and
Qu
xiujie,“Application
of
DDS/FPGA
in
Signal
Generator
Systems”,Modern
Electronics
Technique,2006：78-79.
[2]
Yu
Yong
and
Zheng
Xiaolin,“Design
and
Implementation
of
Direct
Digital
Frequency
Synthesis
Sine
Wave
Generator
Based
on
FPGA”,Journal
of
Electron
Devices,2005：596-599.
[3]
M.A.
Taslakow,“Direct
Digital
Synthesizer
with
improved
spectrum
at
low
frequencies”,2000
IEEE/EIA
International
Frequency
Control
Symposium
and
Exhibition,2000：280-284.
[4]
Yang
Li
and
Li
Zhen,“Multi-wave
shape
Signal
Generator
Based
on
FPGA”,Radio
Engineering,2005：46-48.
[5]
D.J.
Betowski
and
V.
Beiu,“Considerations
for
phase
accumulator
design
for
Direct
Digital
Frequency
Synthesizers”,IEEE
International
Conference
on
Neural
Networks
and
Signal
Processing,2003：176-179.
[6]
J.
Vankka,“Methods
of
mapping
from
phase
to
sine
in
Direct
Digital
Synthesis”,1996
IEEE
International
Frequency
Control
Symposium,1996：942-950.
[7]
K.A.
Essenwanger
and
V.S.
Reinhardt,“Sine
output
DDSs
A
survey
of
the
state
of
the
art”,1998
IEEE
International
Frequency
Control
Symposium,1998：370-376.
附录B
基于DDS参数可调谐波信号发生器的研究
李炜
学院计算机与信息工程河海大学
常州，
213022
，中国[email protected]
张金波
学院计算机与信息工程河海大学
常州，
213022
，中国[email protected]
摘要
谐波信号发生器的频率，相位和谐波比例可调的目的是为检测设备的电源系统。介绍了DDS的原理和设计要求。然后在ROM的压缩算法的基础上阐述了正弦波的对称性。最后，利用Altera的FPGA详细的设计了整个系统，并给出了测试波形。实验结果表明，该系统满足了设计要求。
1简介
一个理想的电力系统是正弦波供电，但实际波形电源往往有许多谐波成分。产生谐波的基本原因是电力系统供电的电气设备的非线性特性。这些非线性负载依靠高次谐波回到电源，使波形的电流和电压的电力系统产生严重的失真。在电力系统的检测领域，标准信号发生器可以模拟电力谐波非常需要标定功率检测设备，如相位检测器，局部放电检测仪，等等。因此，为参数可调谐波信号发生器的研究提供准确的依据和稳定运行的电力检测设备，并具有很大的经济利益和社会价值。
2直接数字频率合成的原理
直接数字合成（
DDS
）是一种在相位的基础上直接合成波形的新的频率合成技术，利用相位和振幅之间的关系，对相位的波形分割和分配有关的地址。在每一个时钟周期，提取这些地址和有关振幅采样。系统中这些被抽样幅度是预期的波形。如果时钟频率是恒定的，频率可调输出信号的地址可有不同提取步骤。
直接数字频率合成器由累加器，存储器，
DAC和低通滤波器组成。在每一个时钟周期，输出相位累加器是由频率控制字累计，高左旋位输出作为地址查询存储器。在ROM中，这些地址被转换为预期波形的抽样振幅。然后数模转换器转换采样振幅为阶梯波。在低通滤波器，平滑阶梯波，输出的是连续的模拟波形。
假设时钟频率是fc，频率控制字为K
，相位累加器为N位，则输出频率fout
=
（
K/2N
）fc，频率分辨率是Δfmin
=
fc/2N
。根据奈奎斯特采样标准，输出频率上限是fmax<0.5fc
。由于非理想特性的低通滤波器，DDS的输出频率上限的是fmax
=
0.4fc。
3方案设计
3.1设计要求
该系统的目标是设计一个谐波信号发生器，其频率相位和谐波比例可调。输出波形是由基波，第三谐波，第五次谐波和第七次谐波构成。频率分辨率是1赫兹。可调范围的初始阶段为0~2π，其图形分辨率为1。可调范围的谐波比例为0~50％，其图形分辨率是1％。根据设计要求，系统时钟频率是15MHz，相位累加器是24位。为了产生最多的EAB,采用211×8位ROM。11位相位控制字是用来满足初始阶段的图形分辨率。7位比例控制字采用正确设定的谐波比例。
3.2ROM的算法
正如人们所知，相位截断误差的主要因素是输出波形畸变。为避免出现这种情况，ROM大小必须成倍增加，但EAB的FPGA是有限的。因此，该算法压缩的ROM基于系统中正弦波的对称性。正弦波一期分为4个部分：[0~π/2]，[π/2~
π]，[π~3π/2]，[3π/2~2π]。使用对称的正弦波，取样振幅的第一部分都存储在ROM。通过地址转换和振幅转换，一期正弦波的采样振幅可以生成。通过这一手段，ROM大小是之前大小的四分之一。在相同的ROM中应用这种方法，采样点可提高4倍。
采样波振幅分块存储在ROM中。输出相位累加器地址是（L+2）-bit。低左旋位是用来查询表的ROM，而高2位是用来识别阶段部分。当最高位为1
，输出的ROM表为对称转换的幅度变换器。当第二个最高位是1
，L型位地址为对称转换的地址转换。
4基于FPGA的系统设计
该系统可分为两个功能模块：正弦波代模块和谐波合成模块。正弦波代模块是系统中关键的部分。它可分为阶段累加器模块和ROM压缩模块。Altera的FPGA
EP2C5Q208C8是该系统的核心组成部分，VHDL语言用来设计整个系统。汇编和仿真使用Quartus
Ⅱ
实现。
4.1正弦波生成模块
相位累加器模块由24位累加器和11位加法器组成的。系统时钟所控制的是9位频率控制字与24位累加器的相加的输出。然后11位相位控制字增加了11位加法器和累加器的输出。高13位的最后结果被用作处理查询正弦数据查询ROM模块。正弦数据查询ROM模块是由地址转换，振幅转换器和ROM模块组成的。13位地址相位累加器模块分为三部分。最高位被用作触发信号的幅度变换器。第二个最高位被用作触发信号的地址转换。低11位是用来查询正弦数据查询ROM模块。然后取样振幅产生正弦波。正弦波信号发生器模块的仿真结果正确。频率控制字设置为50，而相位控制字设置为180。当时钟控制信号变成低电平时，第一个产生数值是ROM模块中地址为180时所对应的正弦波的值。系统时钟的每个上升沿产生波形数据地址所对应的180，181，182，183。其产生的数值分别为76，76，77，77。
4.2谐波合成模块
谐波合成模块完成的是基波，第三次谐波，第五次谐波和第七次谐波的合成。第三次，第五次和第七次谐波数据分别乘以其比例控制字。然后其相乘的结果再加上基波数据。其结果实现的是增强电路模块。因为基于FPGA很难实施多元化的浮点格式，调和比例的划分结果分为分子和分母。分子被定义为比例控制字而分母为100。首先,谐波的数据是乘以这个比例控制字的乘数。然后，这个相乘后的结果再在触发其里除以100。最后，剩下的是余数和商被保存了下来。使用Altera
IP工具、乘法器和除法来实现器谐波合成模块。框图的谐波合成将被显示。谐波合成模块的仿真结果正确。使用2.0ms以内的控制字的话。基波的频率为50赫兹，其初始相位是0度。第三次谐波频率为150赫兹，其初始相位是45度和比例为50%。第五次谐波频率是250赫兹,其初始相位是90度和比例是25%。第七次谐波频率是350Hz,其初始相位是135度和比例是17%。当时钟控制信号转变成低电平时，谐波合成模块开始产生所合成的谐波的数据。
5测试结果
经过系统的设计，整体功能的测试。图7显示双通道正弦波，其频率为50赫兹和相位差是180度。图8显示双通道正弦波，其频率为50赫兹和相位差是120度。图9显示了谐波合成波形，其基波比例为100％，第三谐波的比例是25％，和第5次谐波的比例是10％。试验表明，波形参数可调谐波信号发生器满足了设计要求。
图
7
双通道正弦波（频率
50，相位差是180o
）
图
8
双通道正弦波（频率
50，相位差是120o
）
图9
谐波合成波形
6结论
在电力系统的检测领域，标准信号发生器模拟电力谐波非常精确的标定功率检测设备。为了解决这个问题，介绍了一种频率，相位和谐波比例可调的谐波信号发生器。利用Altera的FPGA实现了整个系统的实施。试验结果表明，调整和稳定精度的参数达到设计要求。这一主题提供了准确的依据，稳定运行的电力检测设备，具有强大的经济利益和社会价值。
参考文献
[
1
]李晓明，曲秀杰，“DDS/FPGA在信号发生器的系统的应用”，现代电子技术，2006年：78-79
[
2
]于育，郑小琳，“基于FPGA的直接数字频率合成正弦波发生器的设计与实现”，电子器件杂志，2005年：596-599
[
3
]M.A.
Taslakow，“改进频谱低频的直接数字频率合成器”，2000年的IEEE
/频率控制的环境影响评估国际研讨会及展览，
2000年：280-284
[
4
]杨力，李镇，“多波形信号发生器的FPGA实现”，无线电工程系，
2005年：46-48
[
5
]
D.J.
Betowski，
V.
Beiu，“思考阶段累加器设计直接数字频率合成器”，IEEE国际会议的神经网络和信号处理，2003年：176-179
[
6
]
J.
Vankka，“以正弦波直接数字频率合成方法测绘阶段”，1996年IEEE国际频率控制专题讨论会，1996年：942-950
[
7
]
K.A.
Essenwanger，
V.S.
Reinhardt，“正弦输出统计局的调查，国家的艺术”，1998年IEEE国际频率控制专题讨论会，1998年：370-376